1. Field
Embodiments described herein relate to an electrically rewritable non-volatile semiconductor storage device and a method of manufacturing the same.
2. Description of the Related Art
As miniaturization technologies are pushed to the limit for improving the bit density of non-volatile semiconductor storage devices such as NAND type flash memory, there is increasing demand for lamination of memory transistors (memory cells). As one example, there has been proposed lamination-type NAND flash memory where memory transistors are configured with vertical transistors. The lamination-type NAND flash memory has a memory string including a plurality of memory transistors connected in series in a lamination direction, and select transistors provided at each end of the memory string.
The lamination-type memory as described above generally performs an erase operation with a GIDL current (Gate Induced Drain Leakage current). That is, the lamination-type memory generates holes by a GIDL current caused by applying high electric fields to the gate end of a select transistor. Then, the lamination-type memory introduces the current produced by holes into the body of memory transistors to increase the potential of that body, and thereby performs an erase operation.
However, if the capacitance of the body of a memory string becomes larger as more memory transistors are connected in series, this may cause an erase operation using GIDL currents to slow down, or make the operation itself difficult.